An 8-bit 2GS/s Time-Interleaved SAR ADC in45nm CMOS Technology

As part of a Mixed-Signal circuit design course, we designed an 8-bit 2GS/s SAR ADC in 45nm technology. The architecture uses several techniques to operate at high speeds such as Time-Interleaving. We also used several techniques to enhance DNL and INL performance. The performance summary is shown in the table below.